• Rana Udayveer Singh

Most Prevalent Integrated Circuit (IC) Design Styles

An Integrated Circuit (IC) is a set of electronic circuits on one small flat piece (or "chip") of semiconductor material (normally silicon). The integration of large numbers of tiny MOS (Metal Oxide Semiconductor) transistors into a small chip resulted in circuits that are orders of magnitude smaller, faster, and less expensive than those constructed of discrete electronic components. The IC's mass production capability, reliability, and building-block approach to integrated circuit design has ensured the rapid adoption of standardized ICs in place of designs using discrete transistors. ICs are now used in virtually all electronic equipment and have revolutionized the world of electronics. Computers, mobile phones, and other digital home appliances are now inextricable parts of the structure of modern societies, made possible by the small size and low cost of ICs.

Broadly, Integrated Circuit (IC) Design can be categorised into Analog and Digital design. Analog IC design has specializations in power IC design and RF IC design. Analog IC design is used in the design of op-amps, linear regulators, phase locked loops, oscillators and active filters and it is more concerned with the physics of the semiconductor devices such as gain, matching, power dissipation, and resistance. Fidelity of analog signal amplification and filtering is usually critical and as a result, analog ICs use larger area active devices than digital designs and are usually less dense in circuitry.

Digital IC design is to produce components such as microprocessors, FPGAs (Field Programmable Arrays), memories (RAM, ROM, and flash) and digital ASICs. Digital IC design focuses on logical correctness, maximizing circuit density, and placing circuits so that clock and timing signals are routed efficiently.

Application Specific IC

An integrated circuit (IC) that is built for a specific use, rather than general use can be named Application Specific IC. For example, a chip designed solely to run a laptop is an ASIC. There are multiple benefits of using application specific ICs:

  • They have higher reliability than general purpose ICs as they are customised to serve a particular function.

  • They have a faster turn-around time (i.e. total time taken between the submission of a program for execution and the return of the complete output to the user.)

  • They are more secure and can’t be exploited easily.

  • They have lower non-recurring costs i.e. the unusual charge, expense or loss that rarely occurs again in the regular period of the function.

  • They show better performance than general purpose ICs.

  • They make more efficient use of board space.

  • It is easier to incorporate unique features and fine-tune the product.

IC Design Styles

1. Full Custom Design: A full custom design means designing integrated circuits by specifying the layout of each transistor and the interconnections between them. This design potentially maximizes the performance of the chip, and minimizes its area, but is extremely labor-intensive to implement, which means higher production costs. This design is limited to ICs that are to be fabricated in extremely high volumes. The time taken to design an IC is long and slow. A full-custom IC includes some logic cells that are customized and all mask layers that are customized. Therefore, full-custom ICs are the most expensive to manufacture and design. For example microprocessors. The major advantage of this design is that while making optimum use of the chip area, it can integrate analog components and pre-designed components, which leads to a higher degree of optimisation in performance. In a full custom design, the entire mask design is done from scratch without the use of any library. However, the development cost of such a design style is high which has propelled the reuse of designs, to reduce design cycle time and development cost.

2. Gate Array Design: A gate array is an approach to the design and manufacture of application-specific integrated circuits (ASICs) which makes use of a prefabricated silicon chip circuit with no particular function which has transistors, standard NAND or NOR logic gates, and other active devices placed at regular predefined positions and manufactured on a wafer, collectively known as the gate array circuit. Some parts of the chip (transistors) are pre-fabricated, and other parts (wires) are custom fabricated according to customer needs and the circuit is accomplished by adding layers of metal that interconnect to the chips. Gate array implementation can be understood as a two-step process, in which the first phase is based on generic masks, resulting in an array of uncommitted transistors on each chip. These uncommitted chips can be stacked for later customization. Since the patterning of metallic interconnects is done at the end of the chip fabrication, the turn-around time is usually short, ranging from a few days to a few weeks.

The above figure shows a corner of a gate array chip which contains bonding pads on its left and bottom edges, diodes for I/O protection, nMOS transistors and pMOS transistors for chip output driver circuits in the neighboring areas of bonding pads, arrays of nMOS transistors and pMOS transistors, underpass wire segments, and power and ground buses along with contact windows.

Further, there are two types of gate array, namely, Channeled Gate Array and Channel-less or Sea-of-Gates Gate Array. Channels are the dedicated areas on a GA chip for intercell routing between rows or columns of MOS transistors. The availability of these routing channels simplifies the interconnections and makes a pattern, even using one metal layer only. These patterns are used to realize basic logic gates that can be stored in a library, and can then be used to customize rows of uncommitted transistors according to the desired connectivity of an electronic circuit. In channeled gate arrays, the interconnections between the logic cells are performed within the predefined channels between the rows of the logic cells.

Using multiple interconnect layers, routing can be achieved over the active cell areas; thus, the routing channels can be removed as in Sea-of-Gates (SOG) chips. Here, the entire chip surface is covered with uncommitted nMOS and pMOS transistors and the connections are made on an upper metal layer on top of the logic cells. In the gate array chip, neighboring transistors can be customized using a metal mask to form basic logic gates. For intercell routing, however, some uncommitted transistors must be sacrificed. This approach results in more flexibility for interconnections, and usually in a higher density.

3. Standard Cell: Standard Cell Design is an approach to designing application specific integrated circuits using mostly digital-logic features. The standard-cells based design is one of the most prevalent full custom design styles which require development of a full custom mask set and is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation. Standard Cell is a group of transistors and inter-connects structures that provide a Boolean Logic function (e.g., AND, OR, XOR, XNOR, inverters) or even a storage function (flip-flop or latch). In this design style, all the commonly used logic cells are developed, characterized, and stored in a standard cell library. A typical library may contain a few hundred cells including inverters, NAND gates, NOR gates, flip-flops etc. There can be multiple implementations for the same components to provide high circuit speed or adequate driving capability for different fanouts, as chosen by the designer.

Inside the input/output (I/O) frame, the chip area contains rows or columns of standard cells. Between cell rows are channels for dedicated inter-cell routing, but they can be reduced or even removed, provided that the cell rows offer sufficient routing space as in the case of Sea-of-Gates, with over-the-cell routing. The physical design and layout of logic cells ensure that when cells are placed into rows, their heights are matched and neighboring cells can be abutted side-by-side, which provides natural connections for power and ground lines in each row.

After chip logic design is done using standard cells in the library, the most challenging task is to place individual cells into rows and interconnect them in a way that meets the desired requirements of design in circuit speed, chip area, and power consumption. For this purpose, many advanced CAD tools have also been developed and are used extensively. The circuit models which include interconnect components can be extracted from the chip layout and used for various timing operations in the circuit. In many VLSI chips, such as microprocessors and digital signal processing chips, standard-cell design is used to implement complex control logic modules. Although the standard-cell design is often called full custom design, in a strict sense, it is somewhat less than fully custom since the cells are pre-designed for general use and the same cells are utilized in many chip designs. The standard cell design chips are more flexible as they include digital as well as analog functions and have a more compact design.

4. Field Programmable Gate Array (FPGA): It can be “field” programmed to work as per the intended design. It means it can work as a microprocessor or graphics card, or even as both at once. FPGA chips contain thousands of logic gates, with programmable interconnects and are ready to be programmed by users for desired functionality. Hardware Description Languages such as VHDL and Verilog are used to create FPGA designs. A typical FPGA chip is made up of several Configurable Logic Blocks (CLB’s), I/O Buffers and are connected with Programmable Interconnects. The CLB’s are primarily made of Look-Up Tables (LUT’s), Multiplexers and Flip-Flops. Apart from CLB’s, and routing interconnects, many FPGAs also contain dedicated hard-silicon blocks for various functions such as Block RAM, DSP Blocks, External Memory Controllers, PLL’s etc. The programming of the interconnects is implemented by the programming of RAM cells whose output terminals are connected to the gates of MOS pass transistors. The general architecture of the FPGA chip is shown in the following figure.

The flow of FPGA Fabrication

1. Design Entry: This can be done in two ways, through schematic or through Hardware Description Language (HDL). Various Tools convert these schematic to HDL or HDL to schematic. Generally, for a complex design, it is better to go with HDL, a quicker, language-based process that eliminates the need to design in lower level hardware, while schematics is a good choice for someone who wishes to design using hardware because it provides more accessibility to the entire system. Schematics are better for low level or smaller designs whereas HDL is better for complex designs.

2. Synthesis: As the design entered by us is in the form of code, it needs to be converted into an actual circuit that we intend to implement. This is done by the synthesis tools such as Vitis, Icarus Verilog, vivado etc. It converts the behavior code into gate level netlist where the entire circuit will be represented in form of gates, flip-flops and multipliers. The interconnections between them are also shown in a netlist. The process begins with a syntax check once you feed in your HDL based design. It is then optimized by the reduction of logic, elimination of redundant logic, and the reduction of the size of the design while simultaneously making it faster to implement. The last step is to map out the technology by connecting the design to the logic, estimating the associated time, and churning out the design netlists which are subsequently saved.

3. Implementation: This step determines the layout of your design and consists of three steps: translate, map, and place & route. The tools used in this step are provided by the FPGA vendors because they have the most accurate knowledge about translating a synthesized netlist to an FPGA. The first step for the tools is to gather all the constraints that are set by the user together with the netlist files. Then the tool maps out the implementation by comparing the resource requirement specified in the files to the resources available on the FPGA being used and then the circuit is divided into the logic blocks. As a result, your entire design is placed in specific logic blocks and is ‘mapped out’ into the FPGA. The next step is to connect and route all the signals according to the constraints set by the user between all the logic blocks and I/O blocks.

4. Program FPGA: The last step in the process is to finally load the mapped out and completely routed design into the FPGA chip. For this reason, we need to generate a Bit-Stream file and this bitstream file is to be dumped onto our FPGA board using a Flash programmer device. When we run our FPGA the board mimics our design functionality. This is the entire process for FPGA based design.

Also in FPGA, there are simulation checks which are done at each level. Behavior simulation is done at the design entry level, Functional simulation is done post synthesis and timing simulation is done at the implementation level.

This design provides fast prototyping and has a very short turn-around time (the time required from the start of the design process to obtaining a fully functional chip). The typical price of FPGA chips is usually higher than other realization alternatives (such as gate array or standard cells) of the same design, but for small-volume production of ASIC chips and fast prototyping, FPGA offers a very valuable option.




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