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  • Kamaldeep Singh

Gate-All-Around (GAA) FET – Going Beyond The 3 Nanometer Mark

An Integrated Circuit (IC) is a set of electronic circuits on one small flat piece (or "chip") of semiconductor material (normally silicon). The integration of large numbers of tiny MOS (MetalOxide Semiconductor) transistors into a small chip resulted in circuits that are orders of magnitude smaller, faster, and less expensive than those constructed of discrete electronic components. The semiconductor industry has been struggling to maintain the rate of chip performance. As an illustration, devices from companies such as Intel and AMD provide no more than a 10-15% performance boost over the previous generation devices. This makes people familiar with the industry question that has the device performance reached its peak? Will the manufacturers and the designers be able to break the existing performance barriers?

However, it is not easy for the companies that are manufacturing these chips as there are challenges associated with reducing the size of the chips.

Though commonly associated with the decline of Moore’s law, there are several factors that influence performance, increased slowdowns, and semiconductor process node size. As a result of the combined effect of physics, and business goals, the electronics industry is fearing a slowdown in the pace of semiconductor device innovation.

However, not everyone is ready to give up just yet. Samsung, a leader in the semiconductor design business, introduced a significant transistor design called Gate-All-Around, or GAA, that aims to live up to Moore's law and possibly continue the advancement in transistor-level semiconductor space. Essentially, GAA provides a rework of the traditional transistor design wherein gate material surrounds the silicon semiconductor channel on four sides instead of being covered by the gate from three sides (as used in current FinFET devices). The two primary benefits of this transistor design are reduction in design size, and increased potential for channel length scaling which attributes to increased transistor density.

Types of FET devices

Figure 1 - Types of FET devices


The first GAAFET was showcased in 1988 by Toshiba which was a vertical nanowire GAAFET, and was called a Surrounding Gate Transistor (SGT). A Gate-All-Around Field Effect Transistor (GAAFET) technology is similar in function to a FinFET transistor but the gate material surrounds the channel from all sides. Generally, based on design, GAAFETs can have two or four gates. Gate-All-Around Field Effect Transistor (GAAFET) technology is believed to be the successor to FinFETs, as it provides better device performance at smaller sizes such as below 7 nm. Nanowire and nanosheet structures are used for the fabrication of GAA transistors. The alignment of the GAAFET structures can be parallel or perpendicular to the substrate depending on the implementation.

Different FET Structures

Figure 2 - Different FET Structures

Figure 2 highlights the difference between the constructions of different types of FET devices. A FinFET device comprises a fin-like structure made up of silicon that extends from the substrate of the device. One end of the fin acts as a source and the other as a drain of the device. The gate is formed over the fin, contacting the fin on the three sides. This creates a channel within the fin. When compared with a traditional FinFET, the gate contacts the channel formed using nanowires and nanosheets on the four sides, providing better control over the channel characteristics. GAAFET semiconductor device does not feature a fin extending from the substrate instead, the device uses layers of Silicon stacked one over the other with spacing.

Though GAAFET semiconductor devices exhibit better performance than the prior FET designs, the manufacturing of these devices comes with increased complexity. The process of a nanowire GAAFET fabrication starts by growing a superlattice of alternating Si and SiGe epitaxial layers. These layers form the basis for the nanowires and nanosheets. An inner dielectric spacer layer is deposited to conserve the drain and source regions and maintain superior administration over the gate width. The empty spaces between the nanosheets are filled with the gate dielectric material and gate metal.