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  • Pankaj Kaushal

VHDL - Understanding the Hardware Description Language

What is VHDL?

VHSIC Hardware Description Language (VHDL) is a programming language used to describe the hardware of a computer. Very High-Speed Integrated Circuit (VHSIC) is an abbreviation. It can be used to explain the structure and behaviour of electronic systems in general, but it's especially well suited to describing the structure and behaviour of digital electronic hardware designs like ASICs and FPGAs, as well as traditional digital circuits.

  • It's a hardware description language, which means it may be used to generate or design digital circuit/system hardware and can describe the behaviour of a digital circuit.

  • It can be used for both synthesis and simulation of digital circuits.

  • It is used to construct digital systems/circuits using Programmable Logic Devices such as CPLD (Complex Programmable Logic Device) or FPGA (Field Programmable Gate Array) (Field Programmable Gate Array)

  • VHDL code (program) is used to implement digital circuits in CPLDs and FPGAs, as well as to fabricate ASICs (Application Specific Integrated Circuit)

Advantages of VHDL

  • When used for systems design, VHDL has the benefit of allowing the behaviour of the needed system to be specified (modeled) and tested (simulated) before the design is translated into physical hardware via synthesis tools (gates and wires).

  • Another advantage is that VHDL may be used to describe a concurrent system. In contrast to procedural computer languages like BASIC, C, and assembly code, where a sequence of statements is performed sequentially one instruction at a time, VHDL is a data-flow language wherein every statement is examined for execution concurrently.

  • A VHDL project can be used for a variety of purposes. A computation block is built once and may be reused in several projects. Many formational and functional block properties, however, may be tweaked (capacity parameters, memory size, element base, block composition and interconnection structure)

  • A VHDL project can be moved around. A computer device project that was designed for one element basis can be transferred to another element base, such as VLSI with multiple methods.

VHDL Design

The first step is to develop VHDL code that meets these requirements. The code must be saved in a text file with the same name as its primary object and the extension “.vhd”. After that, a synthesis tool is used to build the code. During the compilation process, several files are created. The synthesizer breaks down the code into hardware structures that are available inside the chosen device. Each structure inferred by the synthesizer is allocated a specific location within the device during fitting (place and route).

This positioning information is crucial because it has a significant impact on the timing behaviour of the resultant circuit. The program allows the circuit to be completely simulated using the timing information obtained by the fitting procedure.

After the specifications have been completed, the designer may go on to the next phase (implementation), which involves creating a programming file for the device (if using a CPLD or FPGA) or the masks (if using ASICs). The design is completed in the case of CPLDs/FPGAs by downloading the programming file from the computer to the target device.

Basic VHDL Elements - Entity and Architecture

Any circuit's VHDL code is broken down into two sections: On the one hand, the entity describes the circuit's input and output ports. The architecture, on the other hand, explains the circuit's behavior. An entity must be linked to architecture. It is also possible to attach many architectures to the same thing, allowing the programmer to choose from among them.

Entity: A hardware module is described using an entity in VHDL. It's a perspective of the circuit from the outside. Logic gates and multiplexers are examples of entities. It defines the entity's name as well as the interface ports. Ports are signals or terminals that allow other devices to communicate with one another. With entities, at least one architecture should be present.

The internal description of the design entity - its behavior, structure, or a combination of both – is given by architecture. Each entity has its own declaration, which describes the following:

  • Port number

  • Port direction

  • Port types

  • Port timing information

Inputs (in), outputs (out), input-outputs (inout), and buffers are all possible ports for an entity. Inside the architecture, the input ports can only be read, and they can't be changed. On the other hand, the output ports can only be written to, not read from. If an output port or an input port has to be read (for example, to make a choice about its value), they must be created as an inout or a buffer port.

Architecture: In VHDL, the entity-architecture pairs are utilized to fully define the functioning of a circuit. An architecture describes how a circuit works by containing a collection of inner signals, operations, processes, and functions, and it can be structural or behavioural in nature. The entity's architectural statement outlines the entity's underlying functionality. Architecture is always associated with an entity and specifies its behaviour. There are two elements to architecture: a declarative (optional) portion and a statements (code) part. The former can include the same elements as an entity's declarative section, as well as component declarations and configuration requirements. The VHDL statements are inserted in the latter. The name of architecture, like the name of an entity, can be almost any word, even the same name as the entity.

VHDL Architecture supports 4 modeling styles in code structure:

  • Behavioural modeling

  • Structural modeling

  • Data flow modeling

  • Complex/Mixed modeling

Behavioural Modeling: In VHDL's behavioural modeling technique, the designer uses sequential statements to define an entity's behaviour. In terms of syntax and semantics, it's extremely close to high-level programming languages. The use of a process block is the key technique for writing a program in a behavioural style. A process block contains a collection of statements that the VHDL compiler runs in order. Statements within the process block may describe entity's or a portion of the entity's operation. The compiler will execute statements in the same sequence that the designer writes them, which is known as sequential execution. This method of execution is quite similar to C, C++, JAVA, and other high-level programming languages.

Structural Modeling: In VHDL, structural modeling is commonly used for big designs. It enables the designer to create code that can be reused. The designer creates a tiny entity in a separate file that may be used as a component in a bigger entity. Signals can also be used to connect components, allowing big systems to be built from tiny subsystems.

Assume you've already built an adder, a subtractor, a multiplier, and a divider circuit. You've decided to write code for an ALU (Arithmetic & Logic Unit). Then you won't have to start from the beginning. You can utilize such pre-written entities as ALU code components. To utilize them, you just need to map their inputs and outputs to your design specifications.

The initial step in structural modeling is to use the component declaration to create components. The designer specifies the component's name, inputs/outputs, and type of inputs/outputs in the component declaration.

A designer's declared component name may or may not exist in the library. If it isn't in the library, the designer may either develop a component with that name or use a setting to explicitly link any other existing entity to it. The VHDL compiler will not be able to simulate the model otherwise.

Data Flow Modeling: In VHDL data-flow modeling, the designer describes an entity's functionality by specifying the flow of data through each gate. In data-flow modeling, the designer usually employs concurrent signal assignment statements and block statements.

Mixed Modeling: Any mixture of behaviour, data flow, and structural modeling in a single architecture body is known as mixed style modeling. A designer might employ component instantiation statements, concurrent signal assignment statements, and sequential signal assignment statements in a mixed approach to modeling. The mixed style technique, which combines structural and behavioural modeling, is the most prevalent way of modeling big systems. If you wish to develop code for any microprocessor, for example. Make the behavioural code for each block (register, ALU, control, etc.) first, then use the structural way to connect them.

VHDL Technology Applications

IBM: IBM is at the top of the list of top Assignees with 1872 patent families in VHDL technology. IBM design engineers employ a set of Computer-Aided Engineering (CAE) design tools based on the VHSIC Hardware Description Language (VHDL) and created for internal usage, as well as other design automation tools, to create computer hardware. In IBM processor and server development, VHDL technology is used for Logical Design and Functional verification. The logic design is accountable for the description and development of new features for our Z and P microprocessors. Single functions or complete architectures can be included. A logic designer, can generate specifications for functions, units, or subsystems based on client needs and use the hardware description language VHDL to implement their behaviour. The functional VHDL description of the hardware is automatically translated into a structural representation consisting of individual logic gates in a process known as logic synthesis.

Synopsys: Synopsys produces Synplify FPGA synthesis software, which is an industry-standard for producing high-performance and cost-effective FPGA designs. The newest VHDL and Verilog language constructs, including SystemVerilog and VHDL-2008, are supported by Synplify software. The program also supports FPGA designs from Achronix, Intel, Lattice, Microsemi, and Xilinx, all from a single RTL and constraint source. Furthermore, the Synplify synthesis tool offers high performance, quicker runtime, area refinements for cost and power savings, incremental and team-design capabilities, and team-design capabilities for faster FPGA design development. It provides features that help to automate the production of highly dependable designs utilized in medical, automotive, industrial automation, communications, military, and aerospace applications.

Intel: The VHDL (Very High Speed Incorporated Circuit) Hardware Description Language (VHDL) is a high-level, modular language that is fully integrated into the Quartus II software. To produce VHDL Design Files, use the Quartus II Text Editor or any text editor (.vhd). VHDL Design Files can then be used to form full hierarchical projects, or they can be mixed with other types of design files in a hierarchical project. VHDL Design Files can include any number of Quartus II software-supported constructs. They can also include Altera-supplied logic functions, such as primitives and mega functions, as well as user-defined logic functions. Create a Block Symbol File (.bsf) in the Text Editor to represent a VHDL Design File, which may subsequently be included in a Block Design File (.bdf).


VHDL is a programming language for specifying, designing, and describing digital electrical hardware. VHDL was not well suited to abstract system-level simulation before the hardware-software divide. At this level, simulation is generally stochastic and focuses on performance, throughput, queueing, and statistical distributions. VHDL has had some success in this field, but it is better suited to functional rather than stochastic simulation. VHDL may be used throughout the digital hardware design process today, from specification to high-level functional simulation, manual design, and logic synthesis, all the way down to gate-level simulation. In this domain, VHDL tools generally provide an integrated design environment. VHDL isn't well suited to implementation-level design verification tools like analogue simulation, switch level simulation, or worst-case time simulation. VHDL may be utilized to simulate gate level fanout loading effects if coding standards are followed and delay calculation tools are provided. In this area, the VITAL (VHDL Initiative Toward ASIC Libraries) standardization project is ongoing, and it is currently bearing fruit in the form of simulation providers' built-in VITAL support.



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